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Re: [Cryptography] Does RISC V solve Spectre ?



At 06:49 AM 3/24/2018, Jerry Leichter wrote:
>Of course, with the rise of JIT compilation, perhaps this is no longer an issue.
>
>It would make for an interesting experiment.
>
>The JIT compilers I'm aware of do little to accommodate hardware variations - though perhaps they feel they don't need to, because those details don't much matter in the machines and for most code we actually use today.

OpSec?  We need to worry about OpcodeSec!

nVidia's "Dynamic Code Optimization"/"DCO", aka Humpty Dumpty theory of ISA: "When I use an instruction, it means just what I choose it to mean--neither more or less."  Alice: "The question is, whether you can make instructions mean so many different things."

"DCO": Yet more lovely places for malware to hide.  The executing code is "translated" into a microcode buffer, but who gets to be in charge of said translation?

"Those who write the code decide nothing.  Those who execute the code decide everything."  -- apologies to Josef Stalin

I believe that these DCO processors have already been picked up for widespread use in automobiles, including self-driving cars.

What, me worry?
---------
Above is a message I sent over a year ago about nVidia's new "DCO" mechanism, where the standard computer op codes are merely a gentle hint/suggestion about what the CPU should actually do.  Behind the scenes, "DCO" can re-interpret your *hardware op code* to do anything it damn well pleases.  This is the opcode equivalent of *memory maps*, which merely provide gentle hints/suggestions about where to fetch instructions.

See the Youtube video link above for more details.

https://web.stanford.edu/class/ee380/Abstracts/150304.html

Stanford EE Computer Systems Colloquium
4:15PM, Wednesday, March 4, 2015
NEC Auditorium, Gates Computer Science Building Room B3
http://ee380.stanford.edu

Dynamic Code Optimization and the NVIDIA Denver Processor

Nathan Tuck NVIDIA

About the talk:

NVIDIA's first 64-bit ARM processor, code-named Denver, leverages a host of new technologies to enable high-performance mobile computing.  Implemented in a 28-nm process, the Denver CPU can attain clock speeds of up to 2.5 GHz.  This talk will outline the Denver architecture and describe some of its technological innovations.  In particular this talk will discuss some of the motivations and advantages of dynamic code optimization.

Slides:

There not downloadable slides for this presentation available at this time.

Videos:

View Video on YouTube.

http://youtu.be/oEuXA0_9feM

About the speaker:

Nathan Tuck has been a member of the DCO and CPU architecture teams at NVIDIA since 2009.

Nathan has spent his professional career walking a crooked line between hardware and software.  As an engineer, he is most interested in working on systems problems.  Professionally, he is most interested in dynamic environments where he can make a large difference.

Contact information:

Nathan Tuck
NVIDIA

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